并行全比较排序算法&并对角标排序

标签：第一个   random   sed   and   art   时钟周期   amp   generate   scale   

算法基于verilog HDL语言描述：

(1)第一个时钟周期,数据全比较程序

(2)第二个时钟周期,比较值累加

(3)第三个时钟周期,把输入值赋给其对应的排序空间

(4)第四个时钟周期,把排序结果输出

(5)第五个时钟周期,把排序角标输出

source code

`timescale 1ns/1ps
module sort
#(
parameter DATA_WIDTH =8
)
(
input clk,
input rst_n,
input start,
input [DATA_WIDTH-1:0] in0,
input [DATA_WIDTH-1:0] in1,
input [DATA_WIDTH-1:0] in2,
input [DATA_WIDTH-1:0] in3,
input [DATA_WIDTH-1:0] in4,
input [DATA_WIDTH-1:0] in5,
input [DATA_WIDTH-1:0] in6,
output reg [2:0] id0,
output reg [2:0] id1,
output reg [2:0] id2,
output reg [2:0] id3,
output reg [2:0] id4,
output reg [2:0] id5,
output reg [2:0] id6
);

reg add_start;
reg assignm_start;
reg out_start;
reg index_start;
reg complete;

reg [5:0] a,b,c,d,e,f,g;
reg [2:0] tmp0,tmp1,tmp2,tmp3,tmp4,tmp5,tmp6;
reg [DATA_WIDTH-1:0] out0,out1,out2,out3,out4,out5,out6;
reg [DATA_WIDTH-1:0] out_tmp [6:0];

always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
a b c d e f g

add_start end

else if(start)
begin
if(in0 if(in0 if(in0 if(in0 if(in0 if(in0
if(in1 if(in1 if(in1 if(in1 if(in1 if(in1
if(in2 if(in2 if(in2 if(in2 if(in2 if(in2
if(in3 if(in3 if(in3 if(in3 if(in3 if(in3

if(in4 if(in4 if(in4 if(in4 if(in4 if(in4
if(in5 if(in5 if(in5 if(in5 if(in5 if(in5
if(in6 if(in6 if(in6 if(in6 if(in6 if(in6
add_start end
end

always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
tmp0 tmp1 tmp2 tmp3 tmp4 tmp5 tmp6

assignm_start end

else if(add_start)
begin
tmp0 tmp1 tmp2 tmp3 tmp4 tmp5 tmp6

assignm_start end
end

always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
out_tmp[0] out_tmp[1] out_tmp[2] out_tmp[3] out_tmp[4] out_tmp[5] out_tmp[6]

out_start end

else if(assignm_start)
begin
out_tmp[tmp0] out_tmp[tmp1] out_tmp[tmp2] out_tmp[tmp3] out_tmp[tmp4] out_tmp[tmp5] out_tmp[tmp6]

out_start end
end

always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
out0 out1 out2 out3 out4 out5 out6

index_start end

else if(out_start)
begin
out0 out1 out2 out3 out4 out5 out6

index_start end
end

always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
id0 id1 id2 id3 id4 id5 id6

complete end

else if(index_start)
begin
if(out0 == in0) id0 else if(out0 == in1) id0 else if(out0 == in2) id0 else if(out0 == in3) id0 else if(out0 == in4) id0 else if(out0 == in5) id0 else id0
if(out1 == in0) id1 else if(out1 == in1) id1 else if(out1 == in2) id1 else if(out1 == in3) id1 else if(out1 == in4) id1 else if(out1 == in5) id1 else id1

if(out2 == in0) id2 else if(out2 == in1) id2 else if(out2 == in2) id2 else if(out2 == in3) id2 else if(out2 == in4) id2 else if(out2 == in5) id2 else id2
if(out3 == in0) id3 else if(out3 == in1) id3 else if(out3 == in2) id3 else if(out3 == in3) id3 else if(out3 == in4) id3 else if(out3 == in5) id3 else id3

if(out4 == in0) id4 else if(out4 == in1) id4 else if(out4 == in2) id4 else if(out4 == in3) id4 else if(out4 == in4) id4 else if(out4 == in5) id4 else id4
if(out5 == in0) id5 else if(out5 == in1) id5 else if(out5 == in2) id5 else if(out5 == in3) id5 else if(out5 == in4) id5 else if(out5 == in5) id5 else id5

if(out6 == in0) id6 else if(out6 == in1) id6 else if(out6 == in2) id6 else if(out6 == in3) id6 else if(out6 == in4) id6 else if(out6 == in5) id6 else id6

complete end
end
endmodule

仿真平台

`timescale 1ns/1ps
module sort_tb();
parameter DATA_WIDTH =8 ;
reg clk;
reg start;
reg rst_n;
reg [DATA_WIDTH-1:0] in0;
reg [DATA_WIDTH-1:0] in1;
reg [DATA_WIDTH-1:0] in2;
reg [DATA_WIDTH-1:0] in3;
reg [DATA_WIDTH-1:0] in4;
reg [DATA_WIDTH-1:0] in5;
reg [DATA_WIDTH-1:0] in6;
wire [2:0] id0;
wire [2:0] id1;
wire [2:0] id2;
wire [2:0] id3;
wire [2:0] id4;
wire [2:0] id5;
wire [2:0] id6;
parameter t=2;

initial//generate the clock
begin
clk=1‘b1;
forever #(t/2) clk=~clk;
end

initial//generate the rst_n
begin
rst_n=1‘b1;
#(2*t) rst_n=1‘b0;
#(2*t) rst_n=1‘b1;
end

initial//generate the input data
begin
#(10*t) start=1‘b1;
in0={$random}%256;
in1={$random}%256;
in2={$random}%256;
in3={$random}%256;
in4={$random}%256;
in5={$random}%256;
in6={$random}%256;
end

sort
#(
.DATA_WIDTH(DATA_WIDTH)
)
sort_t
(
.clk(clk),
.rst_n(rst_n),
.start(start),
.in0(in0),
.in1(in1),
.in2(in2),
.in3(in3),
.in4(in4),
.in5(in5),
.in6(in6),
.id0(id0),
.id1(id1),
.id2(id2),
.id3(id3),
.id4(id4),
.id5(id5),
.id6(id6)
);

endmodule

并行全比较排序算法&并对角标排序

标签：第一个   random   sed   and   art   时钟周期   amp   generate   scale   

原文地址：https://www.cnblogs.com/p1332668050/p/13347221.html